Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric layers such as silicon dioxide or low-k materials and conductive paths or interconnects made of conductive materials. Copper and copper alloys have recently received considerable attention as interconnect materials because of their superior electro-migration characteristics and low resistivity. Interconnects are usually formed by filling copper, by a metallization process, into features or cavities etched into the dielectric layers. The preferred method of copper deposition is electroplating. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in these stacked dielectric layers can be electrically connected using vias or contacts which may extend from one layer to the other.
In a typical interconnect formation process, first an insulating interlayer is formed on the semiconductor substrate. Patterning and etching processes are performed to form features such as trenches and vias in the insulating layer. Then, thin barrier and copper seed layers are deposited and copper is electroplated to fill the features. Once the plating is over, a chemical mechanical polishing (CMP) step is conducted to remove the excess portions of the copper and barrier layers that are at the top surface of the substrate, leaving conductors only in the features. This way an interconnect structure of copper is formed. These processes are repeated multiple times to manufacture multi-layer interconnects.
An exemplary prior art process can be briefly described with the help of FIGS. 1A and 1B. FIG. 1A shows a substrate 8 which is processed to form an exemplary dual damascene interconnect structure shown in FIG. 1B. In this structure, a via 10 and a trench 12 are first formed in a dielectric layer 14 on the substrate 8, and then filled with copper 16 through electroplating process. Conventionally, after patterning and etching, which form the cavities such as vias and trenches, the dielectric layer 14 is first coated with a barrier layer 18, for example, a Ta/TaN composite layer. The barrier layer 18 coats the dielectric layer to ensure good adhesion and acts as a barrier material to prevent diffusion of the copper into the dielectric layers and into the semiconductor devices. Next, a seed layer (not shown), which is often a copper layer, is deposited on the barrier layer. The seed layer forms a conductive material base for copper film growth during the subsequent copper deposition. As the copper film is electroplated, the copper 16 quickly fills the small via 10 but coats the wide trench and the surface in a conformal manner. When the deposition process is continued, the trench is also filled with copper, but a thick overburden layer ‘t’ is formed over the top surface and a step ‘s’ is formed over the large trench. The excess copper, or overburden needs to be removed from the top surface for the formation of interconnect structure. Removal of such a thick copper layer from the surface presents a problem during the CMP step, which is expensive and time consuming. As shown in FIG. 1B, during the CMP removal of the thick copper layer and then the barrier layer from the top surface, a non-planar surface 20 may be formed of the copper left in the trench. Such non-planar surfaces may form due to the difference in polishing rates between the barrier layer and the copper, or other reasons. The non-planar surface 20, or so-called “dishing effect”, adversely affects the quality of the subsequently deposited layers and the resistance of the line formed by the trench 12.
Some prior art processes attempt to minimize or eliminate the dishing effect by employing multiple CMP steps with different slurries and polishing pads. For example, in one particular prior art process, at a first CMP process step, the bulk copper layer on the substrate is removed down to an initial thickness that is over the barrier layer. The first step is performed in a first CMP station. A second step is performed in a second CMP station to expose a portion of the barrier layer that overlies the dielectric layer. In a third step, the portion of the barrier layer that overlies the insulating layer is removed. The third step is performed in a third CMP station.
In another approach, a first CMP step utilizes selective slurry to remove all of the copper from the top surface region. Then a second CMP step employing non-selective slurry is used to remove the barrier from the top surface, at the same time removing some copper from the features and some of the dielectric. This way dishing is reduced, however, since some copper is lost from the features, resistance of the interconnect lines is increased.
In such prior art processes, multiple CMP steps carried out at multiple CMP stations using multiple consumable sets increase the production time and cost. To this end, there is a need for an alternative, lower cost method of removing overburden conductor off the surface of plated substrates.